1. Field of the Invention
This invention relates to a process for forming embedded metallurgy patterns on a substrate, and more particularly to the fabrication of semiconductor devices employing a process for forming an interconnection metallurgy system embedded in the passivating layer with a planar top surface.
2. Description of the Prior Art
The forming of an interconnection metallurgy system for integrated circuit devices has conventionally been done by blanket depositing a metal layer, forming a photoresist layer on the metal layer, exposing the resist to the desired metallurgy pattern, developing the resist, and subsequently etching the exposed portions of the underlying metal layer to thereby form the interconnection metallurgy system. The pattern was subsequently covered by an insulating layer and another metallurgy pattern formed over same, making contact to the underlying layer through via holes, until the desired interconnection metallurgy system was complete. However, with continued miniaturization of semiconductor integrated circuits to achieve greater component density particularly in large scale integrated circuitry, the metallurgy was made smaller and more dense. The planarity of the surface of the system became a serious consideration in the fabrication of interconnecting systems. Each time a metallurgy pattern is deposited on a surface, the more irregular or non-planar the surface of the overlying insulating layer becomes. In general, after three levels of metallurgy have been deposited, the surface becomes so irregular that additional layers cannot be deposited properly. The irregular surface presents two very important problems which have a direct bearing on the yield and reliability of the resultant system. When a layer of metal is deposited over an irregular surface, the resultant layer becomes thinner over a step portion of the supporting layer. This thinned down portion results in current crowding and possible failure due to electromigration. A further problem is concerned with forming the resist pattern. Clear, distinct exposure and development becomes impossible as the surface becomes more irregular.
One particular processing stage which contributes to the problem of non-planarity is the application of insulating or passivating coatings over surface metallurgy. In these processing stages, the passivating film has been found to follow the contour of the deposited conductor pattern. In other words, a line in the conductor or metallization pattern will result in a corresponding elevation in the covering insulative or passivating layer over the metallization pattern. In integrated circuits having multi-levels of metallization, the cumulative effect of such elevations in the insulation layers is highly undesirable.
For example, a line in the metallization pattern may result in a corresponding elevation in the covering dielectric layer over the metallization pattern. Then, after a subsequent level metallization pattern is deposited onto the covering layer and it, in turn, covered by an additional insulative layer, the upper surface of the additional covering layer will display the cumulative effects of both underlying metallization patterns. In such cases, a "skyscraper" effect results wherein the cumulative metallic lines produce pronounced elevations which render the surface of an uppermost insulative layer so irregular, that the metallization lines deposited over such a layer extend over a very bumpy surface. This tends to produce discontinuities in the metal lines.
In addition, in such structures, it is difficult to design a structure in which a via hole through a given covering layer of dielectric material to an underlying metallization line may be made with consistent control so as to avoid over-etching through the insulative layer under the metallization, thereby shorting out the conductive line through its underlying insulation.
The problems with such elevation and irregularity in integrated circuit levels are discussed in detail in U.S. Pat. No. 3,804,738.
In the prior art, a number of approaches have been proposed for lowering the elevations or steps in such insulative layers, to, thereby, planarize the surface. One approach, as is described in U.S. Pat. No. 3,983,022, and involves resputtering ("sputter polishing") of the elevations.
Although this approach has been effective in planarizing elevations of relatively narrow widths, it is relatively time-consuming. In fact, the time factor becomes so pronounced that the resputtering approach becomes relatively burdensome where the elevations or steps are relatively wide.
Another approach involves masking the depressed areas or valleys with an etch-resistant material such as photoresist through conventional photolithographic techniques, and then etching to remove the uncovered elevations or steps. This approach often runs into problems with photoresist mask alignment. In high density large scale integrated circuits, the dimensions are so minute that difficulties may be encountered in obtaining the exact registration required to completely mask the depressed areas or valleys with photoresist. Any misalignment which leaves a portion of a depressed area exposed could result in an etch through the insulative layer in said depressed area simultaneously with the planarization of the elevated area. This will result in an undesirable short circuit path through the insulative layer in the depressed area.
A further approach of special interest is that disclosed by J. J. Calocino and T. A. Bartush in the IBM-TDB article "Removal of Quartz Spikes Over Metal Lands", page 1381, Vol. 20, No. 4, September 1977. In this approach, surface variations in the form of quartz spikes formed over metallization patterns in quartz layers are planarized by coating the quartz layer with a suitable resist, such as a diazoquinone/novolak resist (eg. Shipley's AZ1350J) and reactive ion etching in an ambient mixture of CF.sub.4 (92%) and oxygen (8%) which will produce an etch ratio of about 1/1 between the resist and the quartz. When the planar removal of the resist reaches the quartz spikes, both are removed concurrently (at substantial equal rates) until planarization of the quartz is obtained. Thereafter "via holes are then opened using a patterned resist layer". As can be seen, the technique provides no solution to the planarization of substrate surface variations due to vertical displacements of both, the insulator layer and the conductor or metallization pattern.